Adaptive Low-Power Zero-Cross Comparator for Discontinuous Current Mode Operated Switching Mode Power Supply

ABSTRACT

A time off estimator and an adaptive controller implemented on an integrated circuit to emulate current dependent zero crossing circuitry to permit improved performance of a buck type switching mode power supply. The time off estimator circuit is enhanced by an automatic correction circuit for the timing of a zero crossing where energy to a reference capacitor returns to zero and is turned off awaiting the next cycle where the capacitor is again charged and discharged.

1. TECHNICAL FIELD

The present disclosure relates to power supplies and more particularlyto low power zero cross comparator for discontinuous current modeoperated switching mode power supply.

2. BACKGROUND

A zero crossing comparator is used in switching mode power supply (SMPS)to detect when current from an inductor in the power supply reaches zeroand at that moment block, or turn off the inductor current. Theprecision, by which the zero crossing comparator operates, affects theefficiency of the power supply. If the current from the inductor isturned off late (after the zero crossing) the current in the inductorgoes negative (overshoot) and a node voltage of the power supply goesabove the input voltage turning on a parasitic diode and pushing theextra charge into Vin. If the current from the inductor is turned offearly, current from the inductor is connected by a parasitic diodeconnected to ground, which increases losses since the voltage across theparasitic diode is higher than in the normal on state.

FIG. 1 is a simplified schematic of a typical buck type switching modepower supply (SMPS). The PMOS transistor P and the NMOS transistor Ndirect the current to and from the inductor L. The node voltage VLX isshown in FIG. 2, wherein the inductor current IL is turned off at thezero current crossing in condition A, late in condition B and early incondition C. Given the variations in the devices that make up thecomponents in FIG. 1 and the very small signal input into the zerocompare circuit ZC, the resulting variations in inductor current IL andthe subsequent output voltage Vout across the load Rload will appearmuch like that in FIG. 2 for a typical production of the circuit.Improvement in the circuit design is needed if a more consistent circuitresponse is required.

US 2004/0027101 A1 (Vinciarelli) is directed to an apparatus comprisinga buck-boost DC to DC switching power conversion, wherein a firstswitching device is interposed between a source and a first terminal ofan inductor and a second switching device is interposed between thesecond terminal of the inductor and the load. U.S. Pat. No. 8,274,266 B2(Englehardt et al.) is directed to a power supply system that comprisesan inductor device and a plurality of switching devices that allow thepower supply to operate in a boost mode. U.S. Pat. No. 8,143,874 B2(Templeton) is directed to a switch mode power supply where anintegrated circuit provides ease of integration with switch mode powersupply (SMPS) designs. U.S. Pat. No. 8,115,459 B2 (Prodic et al.) isdirected to a digitally controlled DC-DC converter with a power stagewith at least one switch and an output capacitor. In U.S. Pat. No.7,893,674 B2 (Mok et al.) a switch mode power supply (SMPS) is directedto a transient recovery circuit to stabilize the circuitry when atransition to a new output is performed. U.S. Pat. No. 7,554,310 B2(Chapuis et al.) is directed to a switch mode voltage regulatorcomprising dual digital control loops. U.S. Pat. No. 7,447,049 B2(Garner et al.) is directed to an SMPS controller using primary sidesensing to detect a point of zero magnetic flux. U.S. Pat. No. 6,879,136B1 (Erisman et al.) is directed to an inductor current emulation circuitfor a switch mode power supply configured such that the inductor currentgoes to zero at least once during a cycle.

SUMMARY

It is an objective of the present disclosure to provide a time off(t_(f)) estimator to determine when switching current is turned off in aswitching mode power supply (SMPS).

It is further an objective of the present disclosure to use an adaptivecontroller to determine the best toff time t_(f).

In the present disclosure a switching mode power supply (SMPS) comprisesa time off estimator and an adaptive controller. The time off estimatorpredicts a time when the flow of energy is turned off in a clock cycleand awaiting the next clock cycle, wherein the reactive element of thepower supply is charged for time t_(r) and then discharged for timet_(f). The reactive element in the present disclosure is a capacitor ina voltage mode circuit used to mimic an inductor in a current modecircuit. An adaptive controller is used to sense over shoot orundershoot of the switching node above or below the supply rails andadjusts a voltage, vRefOffset, to determine the best turn off setting toavoid spikes caused by the turn off time being too long or truncation ofthe signal because the energy from the reactive device is terminated toosoon.

For a buck type SMPS shown in FIG. 1, the toff time estimator is basedon the basic inductor voltage/current relationship.

$\begin{matrix}{{i_{L}(t)} = {\frac{1}{L}{\int{{v_{L}(t)}{t}}}}} & {{EQ}\mspace{14mu} 1}\end{matrix}$

If it is assumed that the voltage across the coil is V_(L)(t) is fixed,V_(L), then EQ. 1 becomes simple multiplication.

$\begin{matrix}{\; {{i_{L}(t)} = {\frac{1}{L}{V_{L} \cdot t}}}} & {{EQ}.\mspace{14mu} 2}\end{matrix}$

When EQ. 2 is applied to the coil current in FIG. 2 during t_(f), therelation for t_(f) is given by

$\begin{matrix}{t_{f} = {\frac{I_{peak} \cdot L}{V_{L}} = \frac{I_{peak} \cdot L}{V_{OUT}}}} & {{EQ}.\mspace{14mu} 3}\end{matrix}$

Where I_(peak) is the maximum peak current when the PMOS was turned offand V_(L) is voltage across the coil which is in the t_(f) period andequal to output voltage V_(OUT). Using the same approach for gettingI_(peak), since we know the t_(r) time and the voltage across theinductor. The voltage applied to the inductor during t_(r) period is thedifference between the input and output voltage.

$\begin{matrix}{I_{peak} = {\frac{1}{L}{\left( {V_{IN} - V_{OUT}} \right) \cdot t_{r}}}} & {{EQ}.\mspace{14mu} 4}\end{matrix}$

If EQ. 3 and EQ 4 are combined, EQ. 5 is obtained, where the t_(f)depends only on known DC voltages and t_(r), which means t_(f) does notdepend on actual inductor value.

$\begin{matrix}{t_{f} = \frac{I_{peak} \cdot \left( {{Vin} - {Vout}} \right) \cdot t_{r}}{V_{OUT}}} & {{EQ}.\mspace{14mu} 5}\end{matrix}$

BRIEF DESCRIPTION OF THE DRAWINGS

This invention will be described with reference to the accompanyingdrawings, wherein:

FIG. 1 is a buck type SMPS power stage of prior art with a zero crossingcomparator;

FIG. 2 is a diagram of prior art of circuit waveforms of the buck typeSMPS power stage;

FIG. 3 is a diagram of a zero crossing time estimator of the firstembodiment of the present disclosure;

FIG. 4 is a diagram of a first variation of the zero crossing timeestimator of the first embodiment of the present disclosure;

FIG. 5 is a diagram of a second variation of the zero crossing timeestimator of the first embodiment of the present disclosure;

FIG. 6 is a diagram of a zero crossing comparator auto-correctioncircuit of the present disclosure;

FIG. 7 is a diagram of the circuit waveforms of the auto-correctioncircuit of the present disclosure;

FIG. 8 is a first variation of the zero crossing comparatorauto-correction circuit of the present disclosure;

FIG. 9 is a second variation of the zero crossing comparatorauto-correction circuit of the present disclosure using digital control;

FIG. 10 is the simulation results obtained from the zero crossingcomparator of the present disclosure.

DETAILED DESCRIPTION

An easy way to model an integrator is by using simple capacitor chargedfrom given current source. The relation between voltage and current inthe capacitor is shown in EQ. 6:

$\begin{matrix}{{v_{C}(t)} = {\frac{1}{C}{\int{{i_{C}(t)}{t}}}}} & {{EQ}.\mspace{14mu} 6}\end{matrix}$

EQ. 6 can be used for modeling a current in the coil as a voltage signalinside an integrated circuit chip. The core of the estimator is shown inFIG. 3. The peak current I_(peak) is given by the voltage dependentcurrent source gm1, which charges the capacitor C during the integratedcircuit transistor PMOS ‘on’ period. The fall time t_(f) is estimated bythe discharging of capacitor C with the voltage controlled currentsource gm2 when integrated circuit transistor NMOS is turned ‘on’.Current sources gm1 and gm2 must be the same value for correctoperation. The voltage controlled current source gm1 has as an input Vinand Vout, where the voltage controlled current source gm2 controls theNMOS transistor and has as in input Vout and ground.

The procedure described herein creates coil-current-like shape voltageon the network node, vCap. The node voltage is compared with referencevoltage vRef during the t_(f) time period, and if the output, ZComp, ofthe comparator triggers the NMOS transistor is turned off. The capacitorC is connected to vRef0 when both switches are off in order to startfrom defined level. The reference Vref applied to the positive terminalof the comparator is the combination of vRef0 and vRefOffset tocompensate for variations in circuit components.

FIG. 4 demonstrates a variation on FIG. 3, wherein the voltagecontrolled current sources are replaced by resistors R1 and R2 with Vinbeing applied to one end of resistor R1. The circuit of FIG. 4 behavessimilarly to the circuit of FIG. 3. The settings for correct operationfor this circuit are R1=R2 and vRef0=Vout. The resistors must be oflarge value and well matched. The signal swing on the vCap node shouldbe kept fairly small to neglect finite variation in current through theresistors.

In FIG. 5 demonstrates another variation on the circuit in FIG. 3 whereA voltage controlled current source gm1 has Vin and ground as input anda second voltages controlled voltage source gm2 is controlled by Voutand circuit ground. The NMOS transistor in FIG. 3 has been eliminated.The reference voltage source vRef0 must have a low output impedancesince vRef0 is loaded by the current VOut*gm2 during the toff period.

The aforementioned zero-crossing comparators works fine stand alone, butthere is no feedback which measure whether the timing is correct. Inorder to determine the timing is correct, a new feed-back is introduced.This feedback simply changes the reference voltage vRef0 by vRefOffsetwhich corrects the timing of the zero-crossing comparator. A simplifiedschematic of the correction circuit is shown in FIG. 6.

It was previously mentioned that if the NMOS is not turned off at righttime the voltage on VLX node (see FIG. 7) goes either below 0V or aboveVIN. The adaptive controller senses the low or high peaks and adjuststhe vRefOffset voltage accordingly. The simplified schematic is shown inFIG. 6, and consists of two comparators C1 and C2, which compare VLXwith VIN and VLX with 0V respectively. The offset voltage Voffset1avoids misbehavior and wrong triggering of the circuit and can bedifferent for each comparator. Output of the two comparators C1 and C2control switches which allow charging and discharging of capacitor Crefwith current I1 or I2. These currents I1 and I2 do not need to be thesame value but it is recommended to keep them same. If the NMOS isturned off too late, the VLX node goes above the VIN and comparator C1turns on the DOWN switch which increases the vRefOffset voltage and thusdecreases the t_(f).

Related vCap and vRef waveforms are shown in FIG. 7. If the NMOS isturned off too early VLX node goes below zero and comparator C2 turns onthe UP switch, which increases the t_(f) time. If the vRef is setcorrectly there is no UP or DOWN signal since the VLX goes neither below0 nor above VIN. This procedure trims-out offset and delay of thecomparator as well.

A modified solution for the auto correction circuit is shown in FIG. 8.This circuit turns on the relay on negative LX pulse only. The crucialthing in this circuit is that the I1 current be significantly lower thanI2. A possible solution of the I1 current source is a switchedcapacitor, which is synchronously charged and then it is connected tothe vRefOffset. This assures precise amount of charge is transferred into the Cref capacitor in each clock-cycle. A similar variation is toomit comparator C2 in FIG. 6 and rely on the positive peak on LX node.However, this solution has potentially slower response than the firstone.

Alternatively, the right part of the circuit can be replaced by digitalas it is shown in FIG. 9. The outputs of the two comparators are fedinto the digital up/down counter, and the output of the digital up/downcounter can be used for direct control of some of the variables in theestimator, gm1, gm2, vRefOffset, and offset of the comparator. Thissolution might be larger than the pure analog solution but brings thepossibility to easily get the digital control signal via digital testmultiplexer for debugging, for example

In FIG. 10 are shown simulation results. The t_(f) time is initiallylonger than it should be so the current goes negative, which appears assmall negative pulses in the ILX—coil current waveform. The circuit thencompensates for the small negative pulses by adjusting the vRef and thesmall negative peaks disappear after few clock-cycles.

It should be noted that the techniques and circuitry shown herein arealso applicable for other SMPS topology, for instance boost andbuck-boost SMPS circuitry.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A switching mode power supply (SMPS), comprising:a) a time off (toff) estimator; b) an adaptive controller; and c) saidestimator predicts a time when energy flow is turned off, wherein saidadaptive controller determines the best toff setting.
 2. The powersupply of claim 1, wherein said time off estimator is formed by a firstvoltage dependent current source to charge a capacitor during an “on”time of a PMOS transistor and a second voltage dependent current sourceto discharge said capacitor during an “on” time for an NMOS transistorand turning off said NMOS transistor when a voltage across the capacitorequals a reference voltage.
 3. The power supply of claim 2, wherein saidfirst voltage dependent current source is replaced by a first resistorconnected to an input voltage and a second resistor replaces said secondvoltage dependent current source connected to circuit ground.
 4. Thepower supply of claim 2, wherein said NMOS transistor is eliminated, thefirst voltage dependent current source is controlled by an input voltageto ground and the second voltage dependent current source is controlledby an output voltage to ground.
 5. The power supply of claim 1, whereinsaid adaptive controller comprises a zero crossing comparator automaticcorrection circuit in which a down comparator circuit selects a downswitch to charge a reference capacitor and an up comparator selects anup switch to discharge said reference capacitor.
 6. The power supply ofclaim 5, wherein said down comparator is eliminated and replaced with a“down” current to charge said reference capacitor, wherein said “up”comparator controls said “up” switch to discharge the referencecapacitor and wherein the “down” current smaller than the “up” current.7. The power supply of claim 1, wherein the adaptive controllercomprises a digitally controlled zero crossing comparator automaticcorrection circuit.
 8. The power supply of claim 7, wherein saiddigitally controlled zero crossing comparator comprises a downcomparator, which compares input voltage plus an offset voltage to apower supply node voltage, and an up comparator, which compares saidnode voltage said offset voltage, to control an up and down digitalcounter to control an offset voltage to a reference capacitor.
 9. Amethod for controlling a power supply, comprising: a) forming anadaptive controller; b) forming a time off estimator c) predicting atime when energy flow in a switching mode power supply is turned off toa storage capacitor for each cycle of charging and discharging of saidcapacitor.
 10. The method of claim 9, wherein forming the time offestimator comprises charging said capacitor with a first voltagedependent current source and then discharging the capacitor with asecond voltage dependent current source and turning off the secondvoltage dependent current source when a voltage across the capacitorequals a reference voltage.
 11. The method of claim 10, wherein thefirst voltage dependent current source is replaced by a first resistorconnected to an input voltage and the second voltage dependent currentsource is replaced by a second resistor connected to ground.
 12. Themethod of claim 10, wherein said the first voltage dependent currentsource is controlled by an input voltage and the second voltagedependent current source is controlled by an output voltage.
 13. Themethod of claim 9, wherein forming an adaptive controller comprises azero crossing comparator automatic correction circuit using a “down”comparator circuit to charge a reference capacitor and an “up”comparator circuit to discharge said reference capacitor to determine azero crossing time.
 14. The method of claim 13, wherein said downcomparator is replaced with a down current smaller than an up currentwherein said up comparator controls the discharge of the referencecapacitor.
 15. The method of claim 9, wherein the adaptive controllercomprises a digitally controlled zero crossing comparator automaticcorrection circuit.
 16. The method of claim 15, wherein said digitallycontrolled zero crossing comparator comprises a down and an upcomparator to drive a digital up and down counter to control variablesof in said estimator.